Repurposing NAND ready/busy pin as completion interrupt

ABSTRACT

A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

BACKGROUND

1. Technical Field

Embodiments generally relate to flash memory devices. More particularly,embodiments relate to the repurposing of a NAND memory device Ready/Busycontact as a completion interrupt.

2. Discussion

Computing systems typically store data to different types of storagemedia and devices. In certain cases, such as in high capacity datastorage situations, multiple NAND flash chips may be coupled to a hostdevice such as a chipset. The chipset can include a Ready/Busy (R/B#)input that is coupled to the R/B# pin of each of the NAND chips. Forexample, there might be two or four NAND chips sharing the same R/B#input to the chipset. If any of the NAND chips has a command inexecution, then the R/B# input is typically pulled low. A particularchallenge with such an approach may be that it is difficult to determinewhen a command has completed for a particular NAND chip, since the R/B#input remains low if commands are still outstanding for other chips thatshare that input. Accordingly, the chipset may need to poll the NANDchips with Read Status Enhanced commands in order to determine whichcommands have completed.

For example, the chipset might poll each NAND chip every microsecond ormore to determine command completion. For a program command, the commandcompletion time may be around 200 microseconds, but may vary widely. Foran erase command, the completion time could be around two millisecondsand may also vary. These times can be 2× to 5× longer with multi-levelcell NAND devices (i.e., devices with more than one bit per cell). Oneissue with polling is that the chipset may waste power (e.g., 200 mW inactive state) when sending out Read Status Enhanced commands on such afrequent basis. Another issue can be performance loss. For example,polling for command completions every microsecond might cause commandsto complete later (e.g., 500 ns) than they normally would.

BRIEF DESCRIPTION OF THE DRAWINGS

The various advantages of the embodiments of the present invention willbecome apparent to one skilled in the art by reading the followingspecification and appended claims, and by referencing the followingdrawings, in which:

FIG. 1 is a block diagram of an example of a computing system accordingto an embodiment;

FIG. 2 is a flowchart of an example of a method of managing flash memorycommands according to an embodiment;

FIG. 3A is a timing diagram of an example of a conventional execution ofa command to perform a read operation; and

FIG. 3B is a timing diagram of an example of execution of a command toperform a read operation according to an embodiment.

DETAILED DESCRIPTION

Embodiments may provide for a method of operating a flash memory devicein which a command to execute an operation is received. The method canalso provide for determining that execution of the operation hascompleted, and pulsing a Ready/Busy (R/B#) contact of the memory devicein response to determining that execution of the operation hascompleted.

Embodiments may also provide for a method of operating a host device inwhich a command is issued to perform an operation on one or more of aplurality of flash memory devices coupled to an R/B# contact of the hostdevice. A pulse can be detected on the R/B# contact of the host device,and a Read Status Enhanced command may be issued to each of theplurality of memory devices in response to detecting the pulse.

Embodiments can also include a system having a plurality of NAND memorydevices and a host device. Each NAND memory device may have an R/B#contact and memory logic to receive a command to execute an operationand determine that execution of the operation has completed. The memorylogic can also pulse the R/B# contact of the memory device in responseto determining that execution of the operation has completed. The hostdevice may include an R/B# contact coupled to the R/B#contact of eachNAND memory device, and host logic to detect the pulse on the R/B#contact of the host device. The host logic can also issue a Read StatusEnhanced command to each of the plurality of NAND memory devices inresponse to detecting the pulse.

Turning now to FIG. 1, a computing system 10 is shown having a processor12, system memory 14, a platform controller hub (PCH) 16, a networkcontroller 18, a plurality of NAND memory devices such as NAND die/chips20 (20 a-20 d), and various other controllers 22. The system 10 could bepart of a mobile platform such as a laptop, personal digital assistant(PDA), wireless smart phone, media player, imaging device, etc., or anycombination thereof. The system 10 may also be part of a fixed platformsuch as a personal computer (PC), server, workstation, etc. Thus, theprocessor 12 may include one or more processor cores 24 and anintegrated memory controller (IMC) 26 configured to communicate with thesystem memory 14. The system memory 14 could include dynamic randomaccess memory (DRAM) configured as a memory module such as a dual inlinememory module (DIMM), a small outline DIMM (SODIMM), etc.

The illustrated PCH 16, sometimes referred to as a Southbridge of achipset, functions as a host device and communicates with the networkcontroller 18, which could provide off-platform communicationfunctionality for a wide variety of purposes such as cellular telephone(e.g., W-CDMA (UMTS), CDMA2000 (IS-856/IS-2000), etc.), WiFi (e.g., IEEE802.11, 1999 Edition, LAN/MAN Wireless LANS), Bluetooth (e.g., IEEE802.15.1-2005, Wireless Personal Area Networks), WiMax (e.g., IEEE802.16-2004, LAN/MAN Broadband Wireless LANS), Global Positioning System(GPS), spread spectrum (e.g., 900 MHz), and other radio frequency (RF)telephony purposes. The other controllers 22 could communicate with thePCH 16 to provide support for user interface devices such as a display,keypad, mouse, etc. in order to allow a user to interact with andperceive information from the system 10.

The NAND chips 20 might be used collectively as a solid state disk (SSD)or a cache memory in which high capacity data storage and/or asignificant amount of parallelism may be desired. The NAND chips 20could also be used as a USB (Universal Serial Bus, e.g., USBSpecification 2.0, USB Implementers Forum) flash storage device. Theremay also be solutions that include NAND controllers implemented asseparate application specific integrated circuit (ASIC) controllersbeing connected to the PCH 16 on other standard buses such as a SerialATA (SATA, e.g., SATA Rev. 3.0 Specification, May 27, 2009, SATAInternational Organization/SATA-IO) bus, or a PCI Express Graphics (PEG,e.g., Peripheral Components Interconnect/PCI Express x16 Graphics150W-ATX Specification 1.0, PCI Special Interest Group) bus.Accordingly, each NAND chip 20 may be configured to communicate with thePCH 16 according to a protocol such as the Open NAND Flash Interface(e.g., ONFI Specification, Rev. 2.2, Oct. 7, 2009) protocol, or othersuitable protocol. In particular, each NAND chip 20 may include aReady/Busy (R/B#) contact (e.g., pin, socket, ball, etc.) 30, memorylogic 32 and a status register (SR) 34, where the NAND chips 20 couldall share a Chip Enable (CE#) output of the PCH 16. In the illustratedexample, the R/B# contact 30 of each NAND chip 20 is coupled to an R/B#contact 28 of the PCH 16.

The memory logic 32 may be configured to receive commands from the PCH16 to execute operations such as program, read and erase operations onthe NAND chip 20. Upon determining that execution of a particularoperation has completed, the memory logic 32 can also pulse the R/B#contact 30 of the NAND chip 20 in response to determining that executionof the operation has completed. In particular, the memory logic 32 mightdetermine that execution of the operation has completed by accessing thestatus register 34 of the NAND chip 20. In one example, accessing thestatus register 34 could return a byte value in a format such as thefollowing format.

TABLE 1 Value 7 6 5 4 3 2 1 0 Status Register WP# RDY ARDY VSP R R FAILCFAIL

In the above example, if the ready bit (RDY) is set to one, then theNAND chip logical unit (LUN) or interleaved address is ready for anothercommand and all other bits in the status value are valid. If RDY iscleared to zero, then the last command issued is not yet complete and SRbit 5:0 are invalid and may be ignored. When caching operations are inuse, then RDY could indicate whether another command can be accepted,and the illustrated array ready bit (ARDY) indicates whether the lastoperation is complete. If ARDY is set to one, then there is no arrayoperation in progress. If ARDY is cleared to zero, then there is acommand being processed (RDY is cleared to zero) or an array operationis in progress. When overlapped interleaved operations or cache commandsare not supported, ARDY may not be used. Pseudocode for behavior of theR/B# signal can be given by,

if (StatusRegister[6] transitions from ‘0’ to ‘1’) then pulse R/B# low

or

if (StatusRegister[5] transitions from ‘0’ to ‘1’) then pulse R/B# low.

Various implementation variants of this feature may utilize only bit 6of the status register (the Ready bit). Other implementations may alsouse bit 5 of the status register (the Array Ready bit). Indeed, animplementation may use both bits so that it is possible for the hostdevice to know both events: a) when the NAND chip may accept a newcommand (StatusRegister[6] transitions high), and b) when an arrayoperation has completed (StatusRegister[5] transitions high). Simplyput, if either ready bit (e.g., RDY or ARDY) is set, the memory logiccan pulse the R/B# contact in order to signal a completion interrupt tothe PCH 16.

FIGS. 3A and 3B demonstrate that the R/B# contact, which is typicallypulled low while an operation is being executed under conventionalapproaches, could instead be pulsed for a relatively short period oftime upon completion of execution of the operation. In particular, FIG.3A shows conventional scheme 36 in which a read command (30 h) is issuedand the R/B# contact of the NAND chip is pulled low for the time periodt_(R), which corresponds to the amount of time the NAND chip takes toexecute the read operation. Typically, the time period t_(R) could be onthe order of 20-30 microseconds. Moreover, in an architecture in whichmultiple NAND chips are ganged together and connected to a common R/B#contact of the host device, the result may be that the host device'sR/B# contact is held low perpetually and conveys little or noinformation to the host device.

Accordingly, FIG. 3B shows a revised scheme 38 in which the R/B# contactof the NAND chip is maintained high until execution of the readoperation is completed, at which time the R/B# contact of the NAND chipis pulsed low. In alternative schemes, the R/B# contact might bemaintained low and pulsed high. In the illustrated example, the pulsehas a duration of 100 approximately nanoseconds, which is substantiallyshorter than the time period t_(R) that corresponds to the approximately20-30 microsecond completion time of a typical read command. The same istrue with regard to the approximately 200 microsecond completion timefor a typical program command, and the approximately 2 millisecondcompletion time for a typical erase command. Other pulse durations maybe used depending upon the circumstances.

Returning now to FIG. 1, the illustrated PCH 16 has host logic 33 todetect the pulse on the R/B# contact 28 and issue a Read Status Enhancedcommand to each of the plurality of NAND chips 20 in response todetecting the pulse. Therefore, the PCH 16 may no longer need to pollthe NAND chips 20 in order to determine which commands have completed.Such elimination of the polling procedure can provide substantial powersavings and performance advantages.

FIG. 2 shows a method 40 of managing flash memory commands. The method40 may be implemented in fixed-functionality hardware using assemblylanguage programming and circuit technology such as ASIC, complementarymetal oxide semiconductor (CMOS) or transistor-transistor logic (TTL)technology, in executable software as a set of logic instructions storedin a machine- or computer-readable medium of a memory such as randomaccess memory (RAM), read only memory (ROM), programmable ROM (PROM),flash memory, firmware, etc., or any combination thereof. Processingblock 42 provides for issuing a command to perform an operation on oneor more of a plurality of flash memory devices coupled to a Ready/Busy(R/B#) contact of a host device. As already noted, the operation couldbe a program operation, a read operation, an erase operation, and so on.The command can be received by the flash memory device at block 44, andillustrated block 46 provides for initiating execution of the operation.The R/B# contact may be maintained high at block 48, and illustratedblock 50 provides for accessing a status register of the flash memorydevice.

If it is determined at block 52 that a ready bit of the status registeris set and/or has transitioned high, block 54 provides for pulsing theR/B# low. As already noted, the ready bit could be a standard ready bitor an array ready bit that may be used for overlapped interleaving orcaching operations. In one example, the pulse has a duration ofapproximately 100 nanoseconds, which may be significantly less than anexecution time of commands to be processed by the flash memory device.Illustrated block 56 provides for detecting the pulse at the host deviceand Read Status Enhanced commands may be issued to each of the flashmemory devices at block 58.

Generally, the NAND chips 20 (FIG. 1) may use floating-gate transistorsthat are connected in a way that resembles a NAND gate: severaltransistors are connected in series, and only if all word lines arepulled high (above the transistors' threshold voltage) is the bit pulledlow. These groups may then be connected via some additional transistorsto a NOR-style bit line array. To read, most of the word lines can bepulled up above the threshold voltage of a programmed bit, while one ofthem is pulled up to just over the threshold voltage of an erased bit.Thus, the series group may conduct (and pull the bit line low) if theselected bit has not been programmed. Other techniques and transistorconfigurations for implementing the NAND chips 20 (FIG. 1) may also beused.

Embodiments of the present invention are applicable for use with alltypes of semiconductor integrated circuit (“IC”) chips. Examples ofthese IC chips include but are not limited to processors, controllers,chipset components, programmable logic arrays (PLA), memory chips,network chips, systems on chip (SoCs), SSD/NAND controller ASICs, andthe like. In addition, in some of the drawings, signal conductor linesare represented with lines. Some may be thicker, to indicate moreconstituent signal paths, have a number label, to indicate a number ofconstituent signal paths, and/or have arrows at one or more ends, toindicate primary information flow direction. This, however, should notbe construed in a limiting manner. Rather, such added detail may be usedin connection with one or more exemplary embodiments to facilitateeasier understanding of a circuit. Any represented signal lines, whetheror not having additional information, may actually comprise one or moresignals that may travel in multiple directions and may be implementedwith any suitable type of signal scheme, e.g., digital or analog linesimplemented with differential pairs, optical fiber lines, and/orsingle-ended lines.

Example sizes/models/values/ranges may have been given, althoughembodiments of the present invention are not limited to the same. Asmanufacturing techniques (e.g., photolithography) mature over time, itis expected that devices of smaller size could be manufactured. Inaddition, well known power/ground connections to IC chips and othercomponents may or may not be shown within the figures, for simplicity ofillustration and discussion, and so as not to obscure certain aspects ofthe embodiments of the invention. Further, arrangements may be shown inblock diagram form in order to avoid obscuring embodiments of theinvention, and also in view of the fact that specifics with respect toimplementation of such block diagram arrangements are highly dependentupon the platform within which the embodiment is to be implemented,i.e., such specifics should be well within purview of one skilled in theart. Where specific details (e.g., circuits) are set forth in order todescribe example embodiments of the invention, it should be apparent toone skilled in the art that embodiments of the invention can bepracticed without, or with variation of, these specific details. Thedescription is thus to be regarded as illustrative instead of limiting.

The term “coupled” is used herein to refer to any type of relationship,direct or indirect, between the components in question, and may apply toelectrical, mechanical, fluid, optical, electromagnetic,electromechanical or other connections. In addition, the terms “first”,“second”, etc. are used herein only to facilitate discussion, and carryno particular temporal or chronological significance unless otherwiseindicated.

Those skilled in the art will appreciate from the foregoing descriptionthat the broad techniques of the embodiments of the present inventioncan be implemented in a variety of forms. Therefore, while theembodiments of this invention have been described in connection withparticular examples thereof, the true scope of the embodiments of theinvention should not be so limited since other modifications will becomeapparent to the skilled practitioner upon a study of the drawings,specification, and following claims.

We claim:
 1. A system comprising: a plurality of NAND memory devices,each NAND memory device having Ready/Busy contact, and memory logic to,receive a command to execute an operation, determine that execution ofthe operation has completed, and pulse the Ready/Busy contact of thememory device in response to determining that execution of the operationhas completed; and a host device including a Ready/Busy contact coupledto the Ready/Busy contact of each NAND memory device, and host logic to,detect the pulse on the Ready/Busy contact of the host device, and issuea read status enhanced command to each of the plurality of NAND memorydevices in response to detecting the pulse.
 2. The system of claim 1,wherein each memory device further includes a status register, thememory logic to access the status register and pulse the Ready/Busycontact of the memory device if a ready bit of the status register isset.
 3. The system of claim 2, wherein the ready bit is an array readybit.
 4. The system of claim wherein the memory logic is to pulse theReady/Busy contact of the memory device low for approximately 100nanoseconds.
 5. The system of claim 4, wherein the memory logic is tomaintain the Ready/Busy contact of the memory device high untilexecution of the operation has completed.
 6. The system of claim 1,wherein the host device is to issue the command to execute theoperation.
 7. The system of claim 6, wherein the operation includes atleast one of a program, read and erase operation.
 8. A method ofoperating a host device comprising: issuing a command to perform anoperation on one or more of a plurality of flash memory devices coupledto a Ready/Busy contact of the host device; detecting a pulse on theRead/Busy contact of the host device; and issuing a read status enhancedcommand to each of the plurality of flash memory devices in response todetecting the pulse.
 9. The method of claim 8, wherein the detectingincludes detecting a low pulse on the Ready/Busy contact.
 10. The methodof claim 9, wherein the low pulse has a duration of approximately 100nanoseconds.
 11. The method of claim 8, wherein the flash memory devicesinclude NAND devices and the operation includes at least one of aprogram, read and erase operation.